The present disclosure relates to a storage apparatus, a memory controller, a control method for the storage apparatus, and a program run for a computer to perform the method. More specifically, the present disclosure relates to a storage apparatus performing data writing, a memory controller, a control method for the storage apparatus, and a program run for a computer to perform the method.
In a previous storage apparatus exemplified by a memory, writing of write data is followed by verification to determine whether the data writing is successful. Herein, the verification is a process performed by the storage apparatus after the writing of write data at a write address. This verification process is to verify the write data stored in advance in the storage apparatus against data read from the write address. When there is no match between these data, a write error is notified to a memory controller.
Such a write error leads to predetermined exception handling. As an example, Japanese Patent Application Laid-Open No. 2003-76615 describes a memory system in which, when receiving a write error after transmission of a write command, a memory controller transmits another write command including a different write address to ask a memory to try again writing of data (hereinafter, referred to as Patent Document 1).